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rev 0.1 june 2005 1/43 1 m29w008et m29w008eb 8 mbit (1mb x 8, boot block) 3v supply flash memory features summary access times: 70ns, 90ns programming time: 10s per byte typical program/erase controller (p/e.c.) ? embedded byte program algorithm ? status register bits and ready/busy output 19 memory blocks ? 1 boot block (top or bottom location) ? 2 parameter and 16 main blocks block, multi-block and chip erase multiple block protection/ temporary unprotection mode erase suspend and resume modes low power consumption ? standby and automatic standby modes 100,000 program/erase cycles per block 20 years data retention ? defectivity below 1ppm/year electronic signature ? manufacturer code: 20h ? m29w008et device code: d2h ? m29w008eb device code: dch ecopack ? tsop40 package figure 1. package tsop40 (n) 10 x 20mm www.st.com
m29w008et, m29w008eb 2/43 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 address inputs (a0-a19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 data input/outputs (dq0-dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 chip enable (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 output enable (g) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 write enable (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 ready/busy output (rb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.7 reset/block temporary unprotect input (rp) . . . . . . . . . . . . . . . . . . . . . . . . .11 2.8 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.9 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 standard bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.3 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.4 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.5 automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.2 block protection and unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 read/reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 auto select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 unlock bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 unlock bypass program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 unlock bypass reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
m29w008et, m29w008eb 3/43 4.8 chip erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9 erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.10 erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 data polling bit (dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 toggle bit (dq6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 error bit (dq5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 erase timer bit (dq3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5 alternative toggle bit (dq2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 appendix a block address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 appendix b block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.1 programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2 in-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
m29w008et, m29w008eb 4/43 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. program, erase times and program, erase endurance cycles. . . . . . . . . . . . . . . . . . . . . 19 table 5. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. device capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. write ac characteristics, w controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 table 12. write ac characteristics, e controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. reset/block temporary unprotect ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. tsop40 - 40 lead plastic thin small outline, 10 x 20mm, package mechanical data . . . 32 table 15. ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16. top boot block addresses, m29w008et . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 17. bottom boot block addresses, m29w008eb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 18. programmer technique bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 19. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
m29w008et, m29w008eb 5/43 list of figures figure 1. package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. block addresses (top boot block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. block addresses (bottom boot block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. ac testing input output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 figure 9. ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. write ac waveforms, w controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 12. write ac waveforms, e controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13. reset/block temporary unprotect ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 14. tsop40 - 40 lead plastic thin small outline, 10 x 20mm, package outline . . . . . . . . . . . 32 figure 15. programmer equipment block protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 16. programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 17. in-system equipment block protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18. in-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1 summary description m29w008et, m29w008eb 6/43 1 summary description the m29w008e is a 8 mbit (1mb x 8) non-volatile flash memory that can be read, erased at block, multi-block or chip level and programmed at byte level. these operations are performed using a single 2.7v to 3.6v v cc supply voltage. for program and erase operations the necessary high voltages are generated internally. the device can also be programmed using standard programming equipment. the memory is divided into blocks that are asymmetrically arranged. both m29w008et and m29w008eb devices have an array of 19 blocks composed of one boot block of 16 kbytes, two parameter blocks of 8 kbytes, one main block of 32 kbytes and fifteen main blocks of 64 kbytes. in the m29w008et, the boot block is located at the top of the memory address space while in the m29w008eb, it is located at the bottom. the memory maps are showed in figure 4: block addresses (top boot block) and figure 5: block addresses (bottom boot block) . each block can be erased and reprogrammed independently so it is possible to preserve valid data while old data is erased. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. erase operations in one block can be temporarily suspended in order to read from or program in blocks that are not being erased. each block can be programmed and erased over 100,000 cycles. each block can be protected independently to prevent accidental program or erase commands from modifying the memory. all previously protected blocks can be temporarily unprotected. in order to meet environmental requirements, st offers this device in a tsop40 (10 x 20mm) ecopack ? package. ecopack ? packages are lead-free and rohs compliant. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. the device is offered in package and supplied with all the bits erased (set to ?1?). table 1. signal names a0-a19 address inputs dq0-dq7 data input/outputs, command inputs e chip enable g output enable w write enable rp reset/block temporary unprotect rb ready/busy output v cc supply voltage v ss ground nc not connected internally
m29w008et, m29w008eb 1 summary description 7/43 figure 2. logic diagram figure 3. tsop connections ai11359 20 a0-a19 w dq0-dq7 v cc m29w008et m29w00eb e v ss 15 g rp rb v ss dq1 dq2 a7 a1 e a4 a3 a11 a17 a14 a15 dq7 a9 a16 g nc dq5 dq3 nc v cc dq4 dq6 a8 w rb a18 nc rp ai11360 m29w008et m29w008eb 10 1 11 20 21 30 31 40 a0 a12 a13 a19 a10 a5 a6 v cc dq0 v ss a2
1 summary description m29w008et, m29w008eb 8/43 figure 4. block addresses (top boot block) fffffh f0000h m29w008et top boot block addresses total of 16 64 kbyte blocks 64 kbyte main block effffh e0000h 64 kbyte main block dffffh d0000h 64 kbyte main block cffffh c0000h 64 kbyte main block bffffh b0000h 64 kbyte main block affffh a0000h 64 kbyte main block 9ffffh 90000h 64 kbyte main block 8ffffh 80000h 64 kbyte main block 7ffffh 70000h 64 kbyte main block 6ffffh 60000h 64 kbyte main block 5ffffh 50000h 64 kbyte main block 4ffffh 40000h 64 kbyte main block 3ffffh 30000h 64 kbyte main block 2ffffh 20000h 64 kbyte main block 1ffffh 10000h 64 kbyte main block 0ffffh 00000h 16 kbyte boot block 8 kbyte parameter block 8 kbyte parameter block 32 kbyte main block fffffh fc000h fbfffh fa000h f9fffh f8000h f7fffh f0000h ai11361
m29w008et, m29w008eb 1 summary description 9/43 figure 5. block addresses (bottom boot block) fffffh f0000h m29w008eb bottom boot block addresses total of 16 64 kbyte blocks 64 kbyte main block effffh e0000h 64 kbyte main block dffffh d0000h 64 kbyte main block cffffh c0000h 64 kbyte main block bffffh b0000h 64 kbyte main block affffh a0000h 64 kbyte main block 9ffffh 90000h 64 kbyte main block 8ffffh 80000h 64 kbyte main block 7ffffh 70000h 64 kbyte main block 6ffffh 60000h 64 kbyte main block 5ffffh 50000h 64 kbyte main block 4ffffh 40000h 64 kbyte main block 3ffffh 30000h 64 kbyte main block 2ffffh 20000h 64 kbyte main block 1ffffh 10000h 64 kbyte main block 0ffffh 00000h 32 kbyte main block 8 kbyte parameter block 8 kbyte parameter block 16 kbyte boot block 0ffffh 08000h 07fffh 06000h 05fffh 04000h 03fffh 00000h ai11362
2 signal descriptions m29w008et, m29w008eb 10/43 2 signal descriptions see figure 2: logic diagram and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a19) the address inputs for the memory array are latched during a bus write operation on the falling edge of chip enable, e or write enable, w . when a9 is raised to v id , either a read electronic signature manufacturer or device code, block protection status or a write block protection or block unprotection is enabled depending on the combination of levels on a0, a1 a6, a12 and a15. 2.2 data input/outputs (dq0-dq7) during bus write operations, the data inputs/outputs input the data to be programmed in the memory array or a command to be written to the command interface. both are latched on the rising edge of chip enable, e or write enable, w . the data inputs/outputs output the data stored at the selected address during a bus read operation, the electronic signature (manufacturer or device codes), the block protection status or the data polling bit (dq7), toggle bits (dq6) and dq2), error bit (dq5) or erase timer bit (dq3) of the status register. outputs are valid when chip enable, e and output enable, g are active. the output is high impedance when the chip is deselected or the outputs are disabled and when rp is low. 2.3 chip enable (e ) the chip enable, e , activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is high, v ih , the memory is deselected and the power consumption is reduced to the standby level. the chip enable, e , can also be used to control write operations to the command register and to the memory array, while w remains low. the chip enable must be forced to v id during block unprotection operations. 2.4 output enable (g ) the output enable, g , gates the outputs through the data buffers during a bus read operation. when g is high, v ih , the outputs are high impedance. g must be forced to v id during block protection and unprotection operations. 2.5 write enable (w ) this write enable, w , controls write operations of the memory?s command interface.
m29w008et, m29w008eb 2 signal descriptions 11/43 2.6 ready/busy output (rb ) the ready/busy pin is an open-drain output that can be used to identify when the memory array can be read. ready/busy is high impedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy becomes high impedance. see table 13: reset/block temporary unprotect ac characteristics and figure 13: reset/block temporary unprotect ac waveforms . during program or erase operations ready/busy is low, v ol . ready/busy will remain low during read/reset commands or hardware resets until the memory is ready to enter read mode. 2.7 reset/block temporary unprotect input (rp ) the reset/block temporary unprotect input, rp, can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been previously protected. a hardware reset is achieved by holding rp low, v il for at least t plpx . after reset/block temporary unprotect goes high, v ih , if the device is in read or standby mode, it will be ready for new operations t phel after the rising edge of rp . if the device is in erase, erase suspend or program mode, the hardware reset will last t plyh during which the rb signal will be held at v il . the end of the memory hardware reset will be indicated by the rising edge of rb . a hardware reset during an erase or program operation will corrupt the data being programmed or the blocks being erased. see table 13: reset/block temporary unprotect ac characteristics and figure 13: reset/block temporary unprotect ac waveforms . holding rp at v id will temporarily unprotect the previously protected blocks in the memory. program and erase operations on all blocks will be possible. the transition of rp from v ih to v id must slower than t phphh . when rp is returned from v id to v ih all blocks temporarily unprotected will be again protected. 2.8 v cc supply voltage the power supply for all operations (read, program and erase). a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc3 2.9 v ss ground v ss is the reference for all voltage measurements.
3 bus operations m29w008et, m29w008eb 12/43 3 bus operations there are 5 standard bus operations that control the device. these are bus read, us write, output disable, standby and automatic standby. see table 2: bus operations , for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect the bus operations. 3.1 standard bus operations 3.1.1 bus read bus read operations are used to output the contents of the memory array, the electronic signature, the status register or the block protection status. both chip enable e and output enable g must be low in order to read the output of the memory. a new bus read operation is initiated either on the falling edge of chip enable, e , or on any address transition with e at v il . see figure 10: read mode ac waveforms , and table 10: read ac characteristics for details of the timing requirements. 3.1.2 bus write bus write operations are used to write to the command interface or to latch input data to be programmed. a valid bus write operation begins by setting the desired address on the address inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. output enable must remain high, v ih , during the whole bus write operation. see figures 11 and 12 , write ac waveforms and tables 11 and 12 , write ac characteristics, for details of the timing requirements. 3.1.3 output disable the data outputs are high impedance when the output enable g is high with write enable w high. 3.1.4 standby the memory is in standby mode when chip enable, e, is high and the program/erase controller is idle. the supply current is reduced to the standby supply current, i cc2 , and the outputs are high impedance, independent of the output enable g or write enable w inputs. 3.1.5 automatic standby if cmos levels (v cc 0.2v) are used to drive the bus and if the bus is inactive (no address transition, e = v il ) during 150ns or more, the memory automatically enters a automatic standby mode where the supply current is reduced to the standby supply current, i cc2 . the inputs/outputs will still output data if a bus read operation is in progress.
m29w008et, m29w008eb 3 bus operations 13/43 3.2 special bus operations additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. these bus operations are intended for use by programming equipment and are not usually used in applications. they require v id to be applied to some pins. 3.2.1 read electronic signature the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes allow programming equipment or applications to automatically match their interface to the characteristics of the m29w008e. the electronic signature is output either by applying the signals listed in tab le 2: b us operations or by issuing an auto select command (see section 4.2: auto select command ). 3.2.2 block protecti on and unprotection each block can be individually protected against accidental program or erase using programming equipment. protected blocks can be unprotected to allow data to be changed. there are two methods available for protecting and unprotecting the blocks, one for use on programming equipment (programmer technique) and the other for in-system use (in-system technique). block protect and chip unprotect operations are described in appendix b: block protection . table 2. bus operations operation e g w rp address inputs a0-a19 dq0- dq7 byte read v il v il v ih v ih cell address data output byte write v il v ih v il v ih command address data input output disable v il v ih v ih v ih xhi-z standby v ih x (1) 1. x = v il or v ih . x (1) v ih xhi-z read electronic signature manufacturer code v il v il v ih v ih a0= v il , a1= v il , a9=v id , others address bits are ?don?t care? 20h device code m29w008et v il v il v ih v ih a0= v ih , a1= v il , a9=v id , others address bits are ?don?t care? d2h m29w008eb dch
4 command interface m29w008et, m29w008eb 14/43 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. failure to observe a valid sequence of bus write operations will result in the memory returning to read mode. the long command sequences are imposed to maximize data security. all commands start with two coded cycles which unlock the command interface. seven commands are available: read/reset, auto select (to read the electronic signature and the block protection status), program, block erase, chip erase, erase suspend and erase resume (see table 3: commands ). 4.1 read/reset command the read/reset command returns the memory to its read mode where it behaves like a rom or eprom, unless otherwise stated. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. the read/reset command can be issued, between bus write cycles before the start of a program or erase operation, to return the device to read mode. once the program or erase operation has started the read/reset command is no longer accepted. the read/reset command will not abort an erase operation when issued while in erase suspend. 4.2 auto select command the auto select command is used to read the manufacturer code, the device code and the block protection status. three consecutive bus write operations are required to issue the auto select command. once the auto select command is issued the memory remains in auto select mode until another command is issued. from the auto select mode the manufacturer code can be read using a bus read operation with a0 = vil and a1 = vil. the other address bits may be set to either vil or vih. the device code can be read using a bus read operation with a0 = vih and a1 = vil. the other address bits may be set to either vil or vih. the block protection status of each block can be read using a bus read operation with a0 = vil, a1 = vih, and a13-a19 specifying the address of the block. the other address bits may be set to either vil or vih. if the addressed block is protected then 01h is output on data inputs/ outputs dq0-dq7, otherwise 00h is output. 4.3 program command the program command can be used to program a value to one address in the memory array at a time. the command requires four bus write operations, the final write operation latches the address and data and starts the program/erase controller. if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given.
m29w008et, m29w008eb 4 command interface 15/43 during the program operation the memory will ignore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in tab le 4: program, erase times and program, erase endurance cycles . bus read operations during the program operation will output the status register on the data inputs/outputs. see section 5: status register for more details. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. note that the program command cannot change a bit set at ?0? back to ?1?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. 4.4 unlock bypass command the unlock bypass command is used in conjunction with the unlock bypass program command to program the memory. when the access time to the device is long (as with some eprom programmers) considerable time saving can be made by using these commands. three bus write operations are required to issue the unlock bypass command. once the unlock bypass command has been issued the memory will only accept the unlock bypass program command and the unlock bypass reset command. the memory can be read as if in read mode. 4.5 unlock bypass program command the unlock bypass program command can be used to program one address in memory at a time. the command requires two bus write operations, the final write operation latches the address and data and starts the program/erase controller. the program operation using the unlock bypass program command behaves identically to the program operation using the program command. a protected block cannot be programmed; the operation cannot be aborted and the status register is read. errors must be reset using the read/reset command, which leaves the device in unlock bypass mode. see the program command for details on the behavior. 4.6 unlock bypass reset command the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. read/reset command does not exit from unlock bypass mode. 4.7 block erase command the block erase command can be used to erase a list of one or more blocks. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller about 50s after the last bus write operation. once the program/erase controller starts it is not possible to select any more
4 command interface m29w008et, m29w008eb 16/43 blocks. each additional block must therefore be selected within 50s of the last block. the 50s timer restarts when an additional block is selected. the status register can be read after the sixth bus write operation. see the status register for details on how to identify if the program/ erase controller has started the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the block erase operation the memory will ignore all commands except the erase suspend command. typical program times are given in table 4: program, erase times and program, erase endurance cycles . all bus read operations during the block erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to ?1?. all previous data in the selected blocks is lost. 4.8 chip erase command the chip erase command can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation appears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands. it is not possible to issue any command to abort the operation. typical program times are given in table 4: program, erase times and program, erase endurance cycles . all bus read operations during the chip erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. the chip erase command sets all of the bits in unprotected blocks of the memory to ?1?. all previous data is lost. 4.9 erase suspend command the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus write operation. the program/erase controller will suspend within the erase suspend latency time after the erase suspend command is issued (see table 4: program, erase times and program, erase
m29w008et, m29w008eb 4 command interface 17/43 endurance cycles ). once the program/erase controller has stopped the memory will be set to read mode and the erase will be suspended. if the erase suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start immediately when the erase resume command is issued. it is not possible to select any further blocks to erase after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. if any attempt is made to program in a protected block or in the suspended block then the program command is ignored and the data remains unchanged. the status register is not read and no error condition is given. reading from blocks that are being erased will output the status register. it is also possible to issue the auto select, during an erase suspend. the read/reset command must be issued to return the device to read array mode before the resume command will be accepted. 4.10 erase resume command the erase resume command must be used to restart the program/erase controller from erase suspend. an erase can be suspended and resumed more than once.
4 command interface m29w008et, m29w008eb 18/43 table 3. commands command (1) 1. commands not interpreted in this table will default to read array mode. length bus write operations (2)(3) 2. x = don't care. pa = program address, pd = program data, ba = block address, ab = additional block. 3. for coded cycles address inputs a15-a19 are don't care. 1st 2nd 3rd 4th 5th 6th 7th add data add data add data add data add data add data add data read/reset (4)(5) 4. a wait of t plyh is necessary after a read/reset command if the memo ry was in an erase or program mode before starting any new operation (see table 10: read ac characteristics ). 5. the first cycles of the read/reset and auto select commands are followed by read operations . any number of read cycles can occur after the command cycles. 1 + x f0h read memory array until a new write cycle is initiated. 3 + 555h aah 2aah 55h 555h f0h read memory array until a new write cycle is initiated. auto select (5) 3 + 555h aah 2aah 55h 555h 90h read electronic signature or block protection status until a new write cycle is initiated. (6)(7) 6. signature address bits a0, a1, at v il will output the manufacturer code (20h). address bits a0 at v ih and a1, at v il will output the device code. 7. block protection address: a0, at v il , a1 at v ih and a13-a19 within the block will output the block protection status. program 4 555h aah 2aah 55h 555h a0h pa pd read data polling or toggle bit until program completes. unlock bypass 3 555h aah 2aah 55h 555h 20h unlock bypass program 2xa0hpapd unlock bypass reset 2x90h x 00h chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h (8) 8. read data polling, toggle bits or rb until erase completes. block erase 6 + 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba 30h ab (9) 9. optional, additional block (ab) addresses must be entered within the erase time-out delay after last write entry, time-out status can be verified through dq3 value (see erase timer bi t dq3 description). when full command is entered, read data polling or toggle bit until erase has completed or is suspended. 30h erase suspend (10) 10. during erase suspend, read and data program fu nctions are allowed in blocks not being erased. 1xb0h read until toggle stops, then read all the data needed from any block(s) not being erased then resume erase. erase resume 1 x 30h read data polling or toggle bits until erase completes or erase is suspended another time.
m29w008et, m29w008eb 4 command interface 19/43 table 4. program, erase times and program, erase endurance cycles parameter min typ (1)(2) 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. max (2) unit chip erase 12 60 (3) 3. maximum value measured at worst case conditions for both temperature and v cc after 100,00 program/erase cycles. s block erase (64 kbytes) 0.8 6 (4) 4. maximum value measured at worst case conditions for both temperature and v cc . s erase suspend latency time 15 25 (3) s program (byte) 10 200 (3) s chip program (byte by byte) 12 60 (3) s program/erase cycles (per block) 100,000 cycles data retention 20 years
5 status register m29w008et, m29w008eb 20/43 5 status register the status of the program/erase controller during command execution is indicated by bit dq7 (data polling bit), toggle bits dq6 and dq2 and error bits dq3 and dq5. any attempt to read the memory array during program or erase command execution will automatically output these five status register bits. the program/erase controller automatically sets bits dq2, dq3, dq5, dq6 and dq7. other bits (dq0, dq1 and dq4) are reserved for future use and should be masked (see table 5: status register bits ). 5.1 data polling bit (dq7) the data polling bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being programmed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the address just programmed output dq7, not its complement. during erase operations the data polling bit outputs ?0?, the complement of the erased state of dq7. after successful completion of the erase operation the memory returns to read mode. in erase suspend mode the data polling bit will output a ?1? during a bus read operation within a block being erased. the data polling bit will change from a ?0? to a ?1? when the program/ erase controller has suspended the erase operation. figure 6: data polling flowchart gives an example of how to use the data polling bit. a valid address is the address being programmed or an address within the block being erased. 5.2 toggle bit (dq6) the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations at any address. after successful completion of the operation the memory returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. if any attempt is made to erase a protected block, the operation is aborted, no error is signalled and dq6 toggles for approximately 100s. if any attempt is made to program a protected block or a suspended block, the operation is aborted, no error is signalled and dq6 toggles for approximately 1s. figure 7: data toggle flowchart gives an example of how to use the data toggle bit.
m29w008et, m29w008eb 5 status register 21/43 5.3 error bit (dq5) the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to ?1? when a program, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to ?0? back to ?1? and attempting to do so will set dq5 to ?1?. a bus read operation to that address will show the bit is still ?0?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1? 5.4 erase timer bit (dq3) the erase timer bit can be used to identify the start of program/erase controller operation during a block erase command. once the program/erase controller starts erasing the erase timer bit is set to ?1?. before the program/erase controller starts the erase timer bit is set to ?0? and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. 5.5 alternative toggle bit (dq2) the alternative toggle bit can be used to monitor the program/erase controller during erase operations. the alternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations from addresses within the blocks being erased. a protected block is treated the same as a block not being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to addresses within blocks not being erased will output the memory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the error. the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased correctly.
5 status register m29w008et, m29w008eb 22/43 table 5. status register bits note: unspecified data bits should be ignored. figure 6. data polling flowchart operation address dq7 dq6 dq5 dq3 dq2 rb program any address dq7 toggle 0 ? ? 0 program during erase suspend any address dq7 toggle 0 ? ? 0 program error any address dq7 toggle 1 ? ? 0 chip erase any address 0 toggle 0 1 toggle 0 block erase before timeout erasing block 0 toggle 0 0 toggle 0 non-erasing block 0 toggle 0 0 no toggle 0 block erase erasing block 0 toggle 0 1 toggle 0 non-erasing block 0 toggle 0 1 no toggle 0 erase suspend erasing block 1 no toggle 0 ? toggle 1 non-erasing block data read as normal 1 erase error good block address 0 toggle 1 1 no toggle 0 faulty block address 0 toggle 1 1 toggle 0 read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai03598 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no
m29w008et, m29w008eb 5 status register 23/43 figure 7. data toggle flowchart read dq6 start read dq6 twice fail pass ai01370c dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6
6 maximum rating m29w008et, m29w008eb 24/43 6 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality documents. table 6. absolute maximum ratings symbol parameter value unit t bias temperature under bias ?50 to 125 c t stg storage temperature ?65 to 150 c t lead lead temperature during soldering (1) 1. compliant with the st 7191395 specification for lead-free soldering processes. 260 (2) 2. not exceeding 250c for more than 30s, and peaking at 260c. c v io (3) 3. v id and v io may undershoot to ?2v during transition and for less than 20ns during transitions. input or output voltage ?0.6 to 5 v v cc supply voltage ?0.6 to 5 v v id (3) identification voltage ?0.6 to 13.5 v
m29w008et, m29w008eb 7 dc and ac characteristics 25/43 7 dc and ac characteristics this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 7: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 7. operating and ac measurement conditions figure 8. ac testing input output waveform parameter m29w008e unit 70 90 min max min max v cc supply voltage 2.73.62.73.6v ambient operating temperature (range 6) ?40 85 ?40 85 c ambient operating temperature (range 1) 0 70 0 70 load capacitance (c l ) 30 100 pf input rise and fall times 10 10 ns input pulse voltages 0 to v cc 0 to v cc v input and output timing ref. voltages v cc /2 v cc /2 v ai09444 v cc 0v v cc/2
7 dc and ac characteristics m29w008et, m29w008eb 26/43 figure 9. ac testing load circuit table 8. device capacitance note: sampled only, not 100% tested. table 9. dc characteristics symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 10 ma i cc2 supply current (standby) e = v cc 0.2v rp = v cc 0.2v 100 a i cc3 (1) supply current (program or erase) program,/ erase controller active 20 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 v cc v cc + 0.3 v v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage cmos i oh = ?100a v cc ?0.4v v v id a9 voltage (electronic signature) 11.5 12.5 v i id a9 current (electronic signature) a9 = v id 100 a v lko (1) 1. sampled only, not 100% tested. supply voltage (erase and program lock-out) 1.8 2.3 v ai09445 0.8v out c l c l includes jig capacitance 3.3k ? 1n914 device under test
m29w008et, m29w008eb 7 dc and ac characteristics 27/43 figure 10. read mode ac waveforms table 10. read ac characteristics symbol alt parameter test condition m29w008e unit 70 90 t avav (1) 1. address are latched on the falling edge of w , data is latched on the rising edge of w . t rc address valid to next address valid e = v il , g = v il min 70 90 ns t avqv (1) t acc address valid to output valid e = v il , g = v il max 70 90 ns t elqx (2) 2. sampled only, not 100% tested. t lz chip enable low to output transition g = v il min 0 0 ns t elqv (1) t ce chip enable low to output valid g = v il max 70 90 ns t glqx (2) t olz output enable low to output transition e = v il min 0 0 ns t glqv (1) t oe output enable low to output valid e = v il max 30 35 ns t ehqz (2) t hz chip enable high to output hi-z g = v il max 25 30 ns t ghqz (2) t df output enable high to output hi-z e = v il max 25 30 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 ns ai09446 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a19 g dq0-dq7 e telqv tehqx tghqz valid
7 dc and ac characteristics m29w008et, m29w008eb 28/43 figure 11. write ac waveforms, w controlled table 11. write ac characteristics, w controlled symbol alt parameter m29w008e unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t elwl t cs chip enable low to write enable low min 0 0 ns t wlwh t wp write enable low to write enable high min 45 50 ns t dvwh t ds input valid to write enable high min 45 50 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whwl t wph write enable high to write enable low min 30 30 ns t avwl t as address valid to write enable low min 0 0 ns t wlax t ah write enable low to address transition min 45 50 ns t ghwl output enable high to write enable low min 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 ns t whrl (1) 1. sampled only, not 100% tested. t busy program/erase valid to rb low max 30 35 ns t vchel t vcs v cc high to chip enable low min 50 50 s ai02192 e g w a0-a19 dq0-dq7 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl
m29w008et, m29w008eb 7 dc and ac characteristics 29/43 figure 12. write ac waveforms, e controlled note: address are latched on the falling edge of e , data is latched on the rising edge of e . ai02193 e g w a0-a19 dq0-dq7 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl
7 dc and ac characteristics m29w008et, m29w008eb 30/43 table 12. write ac characteristics, e controlled symbol alt parameter m29w008e unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t wlel t ws write enable low to chip enable low min 0 0 ns t eleh t cp chip enable low to chip enable high min 45 50 ns t dveh t ds input valid to chip enable high min 45 50 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t ehel t cph chip enable high to chip enable low min 30 30 ns t avel t as address valid to chip enable low min 0 0 ns t elax t ah chip enable low to address transition min 45 50 ns t ghel output enable high chip enable low min 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 ns t ehrl (1) 1. sampled only, not 100% tested. t busy program/erase valid to rb low max 30 35 ns t vchwl t vcs v cc high to write enable low min 50 50 s
m29w008et, m29w008eb 7 dc and ac characteristics 31/43 figure 13. reset/block temporary unprotect ac waveforms table 13. reset/block temporary unprotect ac characteristics symbol alt parameter m29w008e unit 70 90 t phwl (1) t phel t phgl (1) 1. sampled only, not 100% tested. t rh rp high to write enable low, chip enable low, output enable low min 50 50 ns t rhwl (1) t rhel (1) t rhgl (1) t rb rb high to write enable low, chip enable low, output enable low min 0 0 ns t plpx t rp rp pulse width min 500 500 ns t plyh (1) t ready rp low to read mode max 10 10 s t phphh (1) t vidr rp rise time to v id min 500 500 ns ai09447 rb w, rp tplpx tphwl, tphel, tphgl tplyh tphphh e, g trhwl, trhel, trhgl
8 package mechanical m29w008et, m29w008eb 32/43 8 package mechanical figure 14. tsop40 - 40 lead plastic thin small outline, 10 x 20mm, package outline note: drawing is not to scale. table 14. tsop40 - 40 lead plastic thin small outline, 10 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a1.2000 a1 0.050 0.150 0 0 a2 0.950 1.050 0 0 b 0.170 0.270 0 0 c 0.100 0.210 0 0 cp 0.100 0 d 19.800 20.200 1 1 d1 18.300 18.500 1 1 e 0.500??0?? e 9.900 10.100 0 0 l 0.500 0.700 0 0 05 05 n40 40 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1
m29w008et, m29w008eb 9 part numbering 33/43 9 part numbering table 15. ordering information scheme devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m29w008et 70 n 1 e device type m29 operating voltage w = 2.7 to 3.6v device function 008e = 8 mbit (1mb x8), boot block array matrix t = top boot b = bottom boot speed 70 = 70ns 90 = 90ns package n = tsop40: 10 x 20 mm temperature range 1 = 0 to 70 c 6 = ?40 to 85 c option e = ecopack package, standard packing f = ecopack package, tape & reel 24mm packing
9 part numbering m29w008et, m29w008eb 34/43 appendix a block address table table 16. top boot block addresses, m29w008et table 17. bottom boot block addresses, m29w008eb # size (kbytes) address range (x8) 18 16 fc000h-fffffh 17 8 fa000h-fbfffh 16 8 f8000h-f9fffh 15 32 f0000h-f7fffh 14 64 e0000h-effffh 13 64 d0000h-dffffh 12 64 c0000h-cffffh 11 64 b0000h-bffffh 10 64 a0000h-affffh 9 64 90000h-9ffffh 8 64 80000h-8ffffh 7 64 70000h-7ffffh 6 64 60000h-6ffffh 5 64 50000h-5ffffh 4 64 40000h-4ffffh 3 64 30000h-3ffffh 2 64 20000h-2ffffh 1 64 10000h-1ffffh 0 64 00000h-0ffffh # size (kbytes) address range (x8) 18 64 f0000h-fffffh 17 64 e0000h-effffh 16 64 d0000h-dffffh 15 64 c0000h-cffffh 14 64 b0000h-bffffh 13 64 a0000h-affffh 12 64 90000h-9ffffh 11 64 80000h-8ffffh 10 64 70000h-7ffffh
m29w008et, m29w008eb 9 part numbering 35/43 9 64 60000h-6ffffh 8 64 50000h-5ffffh 7 64 40000h-4ffffh 6 64 30000h-3ffffh 5 64 20000h-2ffffh 4 64 10000h-1ffffh 3 32 08000h-0ffffh 2 8 06000h-07fffh 1 8 04000h-05fffh 0 16 00000h-03fffh
9 part numbering m29w008et, m29w008eb 36/43 appendix b block protection block protection can be used to prevent any operation from modifying the data stored in the flash. each block can be protected individually. once protected, program and erase operations on the block fail to change the data. there are three techniques that can be used to control block protection, these are the programmer technique, the in-system technique and temporary unprotection. temporary unprotection is controlled by the reset/block temporary unprotection pin, rp ; this is described in the signal descriptions section. unlike the command interface of the program/erase controller, the techniques for protecting and unprotecting blocks change between different flash memory suppliers. for example, the techniques for amd parts will not work on stmicroelectronics parts. care should be taken when changing drivers for one part to work on another. 9.1 programmer technique the programmer technique uses high (v id ) voltage levels on some of the bus pins. these cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in programming equipment. to protect a block follow the flowchart in figure 15: programmer equipment block protect flowchart . to unprotect the whole chip it is necessary to protect all of the blocks first, then all blocks can be unprotected at the same time. to unprotect the chip follow figure 16: programmer equipment chip unprotect flowchart . table 18: programmer technique bus operations , gives a summary of each operation. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. 9.2 in-system technique the in-system technique requires a high voltage level on the reset/blocks temporary unprotect pin, rp . this can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the flash has been fitted to the system. to protect a block follow the flowchart in figure 17: in-system equipment block protect flowchart . to unprotect the whole chip it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. to unprotect the chip follow figure 18: in- system equipment chip unprotect flowchart . the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
m29w008et, m29w008eb 9 part numbering 37/43 table 18. programmer technique bus operations operation e g w address inputs a0-a18 data inputs/outputs dq7-dq0 block protect v il v id v il pulse a9 = v id , a13-a19= block address others = x x chip unprotect v id v id v il pulse a9 = v id , a13 = v ih , a16 = v ih others = x x block protection verify v il v il v ih a0 = v il , a1 = v ih , a6 = v il , a9 = v id , a13-a19= block address others = x pass = 01h retry = 00h block unprotection verify v il v il v ih a0 = v il , a1 = v ih , a6 = v ih , a9 = v id , a13-a19= block address others = x retry = 01h pass = 00h
9 part numbering m29w008et, m29w008eb 38/43 figure 15. programmer equipment block protect flowchart address = block address ai09448 g, a9 = v id , e = v il n = 0 wait 4s wait 100s w = v il w = v ih e, g = v ih , a0, a6 = v il , a1 = v ih a9 = v ih e, g = v ih ++n = 25 start fail pass yes no data = 01h yes no w = v ih e = v il wait 4s g = v il wait 60ns read data verify protect set-up end a9 = v ih e, g = v ih
m29w008et, m29w008eb 9 part numbering 39/43 figure 16. programmer equipment chip unprotect flowchart protect all blocks ai09449 a6, a13, a16 = v ih (1) e, g, a9 = v id data w = v ih e, g = v ih address = current block address a0 = v il , a1, a6 = v ih wait 10ms = 00h increment current block n = 0 current block = 0 wait 4s w = v il ++n = 1000 start yes yes no no last block yes no e = v il wait 4s g = v il wait 60ns read data fail pass verify unprotect set-up end a9 = v ih e, g = v ih a9 = v ih e, g = v ih
9 part numbering m29w008et, m29w008eb 40/43 figure 17. in-system equipment block protect flowchart ai09450 write 60h address = block address a0 = v il , a1 = v ih , a6 = v il n = 0 wait 100s write 40h address = block address a0 = v il , a1 = v ih , a6 = v il rp = v ih ++n = 25 start fail pass yes no data = 01h yes no rp = v ih wait 4s verify protect set-up end read data address = block address a0 = v il , a1 = v ih , a6 = v il rp = v id issue read/reset command issue read/reset command write 60h address = block address a0 = v il , a1 = v ih , a6 = v il
m29w008et, m29w008eb 9 part numbering 41/43 figure 18. in-system equipment chip unprotect flowchart ai09451 write 60h any address with a0 = v il , a1 = v ih , a6 = v ih n = 0 current block = 0 wait 10ms write 40h address = current block address a0 = v il , a1 = v ih , a6 = v ih rp = v ih ++n = 1000 start fail pass yes no data = 00h yes no rp = v ih wait 4s read data address = current block address a0 = v il , a1 = v ih , a6 = v ih rp = v id issue read/reset command issue read/reset command protect all blocks increment current block last block yes no write 60h any address with a0 = v il , a1 = v ih , a6 = v ih verify unprotect set-up end
10 revision history m29w008et, m29w008eb 42/43 10 revision history table 19. document revision history date version revision details 21-jun-2005 0.1 first issue.
m29w008et, m29w008eb 43/43 information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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